1. Field of the Invention
The invention generally relates to field effect transistors and, more particularly, to a trigate field effect transistor structure and a method of forming the structure.
2. Description of the Related Art
Integrated circuit design decisions are often driven by device scalability and manufacturing efficiency. For example, multi-gated non-planar field effect transistors (FETs), such as fin-type FETs (finFETs) or trigate FETs, were developed to provide scaled devices with faster drive currents and reduced short channel effects over planar FETs. A finFET is a non-planar transistor in which the channel region is formed at the center of a thin semiconductor fin with the source/drain regions at opposing ends. Gates are formed on the opposing sidewalls of the semiconductor fin adjacent to the channel region. A trigate FET has a similar structure to that of finFET; however, the semiconductor fin width and height are such that gates can be formed on three sides of the channel region, including the top surface and the opposing sidewalls. A trigate FET offers additional performance leverage over a planar FET and particularly, better gate control, due to the two-dimensional effect of gate wrapping around the channel corners where the top surface and opposing sidewalls meet. However, this performance advantage is reduced by the horizontal and vertical channel planes at the top surface and opposing sidewalls of the channel region, respectively, which exhibit high parasitic capacitances. It would be advantageous over the prior art to provide a trigate FET that emphasizes the current carrying capability of the channel corners, while minimizing the parasitic capacitance exhibited in the channel planes.